We're Hiring Core Systems Engineers
Build the silicon runtime for autonomous AI.
We strip away virtualization layers, CPU dispatch bottlenecks, and memory overhead so reasoning agents can run at hardware line rate. Work directly with B200/H100 clusters and early equity.
Location: Remote (US / Global)
Team: Core Systems & Silicon
Compensation: Top-of-Market + Heavy Equity
Senior Inference Systems Engineer
Engineering
Full-time
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Remote
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C++20 / Rust / Triton / Distributed Systems
// Mission
You will design, optimize, and maintain the runtime serving engine that powers MetalOps. You'll eliminate framework overhead, optimize dynamic KV caches, and execute sub-millisecond speculative verification pipelines for autonomous coding agents.
// What You'll Do
- Architect low-latency continuous batching and dynamic tensor-parallel scheduling engines.
- Implement hardware-native speculative decoding (parallel block drafting, dynamic drafting trees).
- Optimize KV-cache memory footprints (paged attention, FP8 quantization, memory coalescing across HBM/SRAM).
- Build profiling passes and real-time trace visualizers for Time-to-First-Token (TTFT) and decode latency.
// Qualifications
- 4+ years building high-performance distributed systems in C++20/Rust and Python.
- Production experience with LLM serving architectures (vLLM, SGLang, TensorRT-LLM, or custom engines).
- Working knowledge of high-bandwidth networking (GPUDirect RDMA, InfiniBand, RoCE).
- Profiling proficiency with
nsys,ncu, or PyTorch profilers to identify memory bus stalls.
GPU Kernel Engineer (CUDA / Triton / SASS)
Hardware & Silicon
Full-time
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Remote
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OpenAI Triton / CUDA C++ / PTX / SASS
// Mission
You will write the code that directly drives the silicon. You will design fused persistent megakernels, hand-tune GEMM operations for NVIDIA Hopper and Blackwell architectures, and eradicate memory roundtrips to global HBM.
// What You'll Do
- Design, benchmark, and deploy custom fused kernels using Triton, CUDA C++, and PTX/SASS.
- Build persistent megakernels that keep compute graphs resident in Streaming Multiprocessors (SMs).
- Maximize SRAM and register reuse for attention layers, RMSNorm, and dynamic Mixture-of-Experts routing.
- Co-design automated kernel search loops that iterate tile dimensions and shared memory allocations in parallel.
// Qualifications
- Production expertise writing high-performance GPU kernels in CUDA C++ or OpenAI Triton.
- Deep architectural understanding of modern GPU microarchitectures (H100/H200, B200).
- Experience inspecting assembly (PTX/SASS) to resolve register spills, warp divergence, and latency stalls.
- Fluency in low-level matrix mathematics and tensor layout optimizations.